`default_nettype none

module clk_freq_m #(
    parameter [31:0] MUL_CP_I = 1,
    parameter [31:0] DIV_CP_I = 3
) (
    input rst_w_ni,
    input clk_w_i,

    output clk_w_o
);
    localparam [31:0] COUNTER_WIDTH_CP_L = $clog2(MUL_CP_I + DIV_CP_I);

    wire [COUNTER_WIDTH_CP_L-1:0] pec_wp_l;
    wire [COUNTER_WIDTH_CP_L-1:0] nec_wp_l;
    wire pec_w_l;
    wire nec_w_l;

    edge_counter_clk_m #(
        .BEFORE_EDGE_CP_I(0),
        .MUL_CP_I(MUL_CP_I),
        .DIV_CP_I(DIV_CP_I)
    ) pecc_i_l (
        .rst_w_ni(rst_w_ni),
        .clk_w_i(clk_w_i),
        .counterpart_wp_i(nec_wp_l),

        .counter_wp_o(pec_wp_l),
        .edge_clk_w_o(pec_w_l)
    );

    edge_counter_clk_m #(
        .BEFORE_EDGE_CP_I(1),
        .MUL_CP_I(MUL_CP_I),
        .DIV_CP_I(DIV_CP_I)
    ) necc_i_l (
        .rst_w_ni(rst_w_ni),
        .clk_w_i(clk_w_i),
        .counterpart_wp_i(pec_wp_l),

        .counter_wp_o(nec_wp_l),
        .edge_clk_w_o(nec_w_l)
    );

    assign clk_w_o = pec_w_l ^ nec_w_l;
endmodule
